From: Miroslav Velev <mvelev@gmail.com>
Call for Papers
CFV'09: Sixth International Workshop on Constraints in Formal
Verification
Grenoble, France, June 25, 2009.
A satellite event of the 21st International Conference on
Computer Aided Verification (CAV'09)
CFV'09 web site: http://www.miroslav-velev.com/cfv09.html
Abstract submission deadline: April 15
Paper submission deadline: April 22
Overview
Formal verification is of crucial significance in the development of
hardware and software systems. In the last few years, tremendous
progress was made in both the speed and capacity of constraint
technology. Most notably, SAT solvers have become orders of magnitude
faster and capable of handling problems that are orders of magnitude
bigger, thus enabling the formal verification of more complex computer
systems. As a result, the formal verification of hardware and software
has become a promising area for research and industrial applications.
The main goals of the Constraints in Formal Verification workshop are
to bring together researchers from the CSP/SAT and the formal
verification communities, to describe new applications of constraint
technology to formal verification, to disseminate new challenging
problem instances, and to propose new dedicated algorithms for hard
formal verification problems.
This workshop will be of interest to researchers from both academia
and industry, working on constraints or on formal verification and
interested in the application of constraints to formal verification.
Scope
The scope of the workshop includes topics related to the application
of constraint technology to formal verification, namely:
Delivery
The workshop is scheduled for June 25, 2009. It will be
structured to allow ample time for discussion and demonstration of new
tools and new problem instances.
Submissions
Submissions should be in the LNCS format and in one of the following types:
Important Dates
The important dates for the workshop are as follows:
Invited Speakers
Bernd Becker, University of Freiburg, Germany
Talk title: SAT and SMT Solving in a Multi-Core Environment
Workshop Chair
Miroslav Velev, Aries Design Automation, U.S.A.
Masahiro Fujita, University of Tokyo, Japan
Program Committee
Jay Bhadra, Freescale, U.S.A.
Sérgio Vale Aguiar Campos, Universidade Federal de Minas Gerais, Brazil
Maciej Ciesielski, University of Massachusetts, U.S.A.
Goerschwin Fey, University of Bremen, Germany
Alex D. Groce, NASA-JPL, U.S.A.
Michael Hsiao, Virginia Tech, U.S.A.
Chung-Yang (Ric) Huang, National Taiwan University, Taiwan
John Franco, University of Cincinnati, U.S.A.
Priyank Kalla, University of Utah, U.S.A.
Shin-ichi Minato, Hokkaido University, Japan
Steve Prestwich, University College Cork, Ireland
Andreas Veneris, University of Toronto, Canada
Last updated: Nov 21 2024 at 12:39 UTC